To reduce variations in products such as handheld radios used in wireless communication systems, manufacturers of components strive to create modules capable of handling many frequency bands (multi-band) in a single hardware solution. Modules such as modulators, demodulators, and signal amplifiers have multi-band capabilities. However, the local oscillator necessary for frequency translation has traditionally been difficult to make multi-band while still meeting the phase jitter and error vector magnitude (EVM) requirements for radio receivers or transmitters used in digital communications. Conventional systems require unique local oscillator modules for each frequency to meet the phase jitter and EVM requirements.
Traditional methods of achieving frequency flexibility result in several compromises. For example, a direct digital synthesizer (DDS) uses digital techniques to generate a frequency tunable output signal referenced to a fixed-frequency clock source. A DDS may comprise a numerically controlled oscillator (NCO) with a voltage controlled crystal oscillator (VCXO) used as a reference to a phase locked loop (PLL). Tuning of the DDS output signal may be accomplished by tuning the VCXO of the NCO. VCXO tuning may be achieved by configuring dividers, N and M, to scale a desired frequency and a reference frequency to a common comparison frequency. A DDS may also comprise a digital-to-analog converter (DAC) to convert the desired frequency into an analog signal.
The width of a VCXO's frequency tuning range may impact phase noise present in the DDS output signal. A wider VCXO tuning range results in higher phase noise, and a narrower tuning range results in lower phase noise. This limitation may restrict a traditional DDS to a narrow tuning range.
In some DDSs, the PLL may only scale the desired frequency (N is some integer greater than one) but not the reference frequency (M equals one). This scenario may result in frequency steps at multiples of the reference frequency only, which may limit the target frequency to an integer multiple of the VCXO. This limitation results in a trade-off between phase noise and frequency resolution. Lowering the reference frequency may result in higher ultimate phase noise because of the higher multiplication factor needed to reach the desired frequency.
To achieve greater tuning flexibility, some DDS may scale both the desired frequency (divide by N) and the reference frequency (divide by M) to achieve an N/M ratio of the desired and reference frequencies. This may result in tuning flexibility with a higher VCXO frequency, however it also results in spurious outputs related to the N/M ratio. The spurious outputs may change with the configured frequency. Thus, phase noise of a conventional DDS is a function of the desired output frequency relative to the reference clock and the DAC. Additionally, the output frequency of a conventional DDS may be limited to less than or half the frequency of the reference clock.
Conventional systems also have difficulty synthesizing frequency independent phase locked clocks. Traditionally, multiple clocks may be generated by multiple PLLs all locked to a common reference frequency. However, those multiple clocks may experience phase wander, even though they are locked to a common reference frequency, because of slight differences in the multiple active circuits (e.g., phase detectors, frequency dividers, etc.) used to generate each clock. Circuits driven by these multiple clocks must be designed with complicated logic to compensate for the phase wander.